The present application relates to load control apparatus and, more particularly, to novel improved resistance load sampling and control circuitry in which comparator input offset errors are substantially cancelled.
It is often desirable to operate a lower-voltage load from a higher-voltage source periodic waveform. Typically, such loads are resistive and have a significant resistive temperature coefficient. When this type of load, such as a lamp, resistance heater element and the like, is to be energized from A.C. mains, less than the full mains voltage is required thereacross for proper operation, and a power switching device is included in series with the load, across the mains, for controlling load current conduction. In such cases, a highly-efficient low-voltage power supply is required for energizing the load. It is known to monitor the load resistance and provide for closed-loop control of the non-zero-temperature-coefficient load resistance. Apparatus for achieving such control is disclosed and claimed in my allowed application Ser. No. 382,875, filed May 28, 1982 now U.S. Pat. No. 4,421,993, and in another co-pending application Ser. No. 432,000, filed Oct. 1, 1982 now U.S. Pat. No. 4,461,990, both of which applications are assigned to the assignee of the present application and incorporated in their entireties herein by reference. The resistance comparators disclosed and claimed therein, as well as many other electronic circuits, require the analog comparison of relatively low-level signals on the order of several tens, or hundreds, of millivolts. In both applications, the discrete resistance comparator means requires that a pair of analog comparators be utilized. One comparator provides an output state change when a voltage, proportional to the load voltage, crosses a fixed reference voltage level, while the second comparator provides an output state change when a second voltage, proportional to the load current, crosses a fixed, typically the same, reference voltage level. Since the voltage-proportional-to-current may be limited in magnitude, by allowable power dissipation in a sampling resistance placed in series with the load, to about 100 millivolts, an error of about 1 percent occurs for each millivolt of differential offset drift between the two comparators. Differential offset drift can be controlled utilizing relatively high-quality comparators operating over a moderate temperature range; however, large and intolerable errors result if custom or semicustom integrated circuits, particularly utilizing MOS devices, are utilized to realize a reduced-cost discrete resistance comparator utilizing a pair of analog comparators therein. The error in such use results from the well-known input offset drift of comparators with temperature.
It has been suggested to solve the input offset drift problem by utilization of a single comparator which is switched to alternately sample voltage and current at a rate which is relatively fast when compared to the A.C. mains line frequency (e.g. 60 Hz. in the United States). Utilization of a single comparator can eliminate the offset problem, but degrades discrete resistance comparator performance due to slew rate and other operational amplifier limitations. This is true because the ideal resistance measurement requires that voltage and current be measured at the same relative time in the applied source waveform cycle. Utilizing a single comparator, the load voltage and load current samples are separated by some small switching time, e.g. 10 microseconds, which results in the current and voltage samples occurring at different points on the source waveform cycle, e.g. about 0.22.degree. apart. During this small switching interval, the indicated load resistance has then changed by some amount, e.g. about 0.22 percent, between the current and voltage samples and results in an apparent hysteresis, or deadband, which contributes unwanted random data about the resistance control point. It has been suggested to utilize a faster sample clock rate to reduce these effects, but present MOS comparator circuits have slew rate limitations which already contribute to the error at the present sampling rates and provide slew rate limitations which prevent increasing the sampling rate thereover.
Accordingly, it is desirable to continue to utilize a pair of analog comparators, each operating upon a sample of a different one of the load current and voltage waveforms, and to provide circuitry in which any change with respect to the desired comparison level in input offset of either of the two comparators is reduced or, more preferably, substantially cancelled.